1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device capable of concurrently electrically performing a data write or erasure operation and a data read operation.
2. Description of the Related Art
In usual operation of a flash EEPROM (one-chip flash EEPROM with simultaneously erasable blocks), a write or erasure operation is performed to or from an arbitrary memory cell block while no other memory cell block is accessed. A write operation usually requires as long a time as several microseconds to ten microseconds, and an erasure operation requires as long a time as several hundred milliseconds to one second. A data write operation and a data erasure operation of a flash EEPROM need to be performed at a higher speed in order to conform to the recent improvement in the operation speed of microprocessors.
For fulfilling such a need, a technology for reading data from an arbitrary memory cell block while writing or erasing data to or from another memory cell block is disclosed in, for example, Japanese Laid-Open Publication No. 6-180999 entitled xe2x80x9cFloating gate nonvolatile memory with reading while writing capabilityxe2x80x9d, Japanese Laid-Open Publication No. 7-281952 entitled xe2x80x9cNonvolatile semiconductor storagexe2x80x9d, Japanese Laid-Open Publication No. 5-54682 entitled xe2x80x9cNonvolatile semiconductor memoryxe2x80x9d, and Japanese Laid-Open Publication No. 10-144086 entitled xe2x80x9cNon-volatile semiconductor memory devicexe2x80x9d.
A nonvolatile semiconductor memory device disclosed in Japanese Laid-Open Publication No. 10-144086 filed by the assignee of the present application will be described with reference to FIG. 6. FIG. 6 is a block diagram illustrating a circuit structure of a conventional nonvolatile semiconductor memory device 40. The nonvolatile semiconductor memory device 40 includes a one-chip flash EEPROM with simultaneously erasable blocks.
As shown in FIG. 6, the nonvolatile semiconductor memory device 40 includes two write circuits 41 and 42, two sensing amplifiers 43 and 44, a plurality of memory cell array blocks MA (MA1, MA2, . . . , MAk), a plurality of column decoders YD (YD1, YD2, . . . , YDk), two row decoders XD1 and XD2, and a plurality of switching circuits SW (SW1, SW2, . . . , SWk-1).
The write circuit 41 is connected to each of the plurality of column decoders YD1 through YDk via a data bus DB-1. The write circuit 42 is connected to each of the plurality of column decoders YD1 through YDk via a data bus DB-2. The plurality of column decoders YD1 through YDk are each connected to the sensing amplifier 43 through the data bus DB-1. The plurality of column decoders YD1 through YDk are each connected also to the sensing amplifier 44 through the data bus DB-2.
The plurality of memory cell array blocks MA1 through MAk are respectively provided in correspondence with the plurality of column decoders YD1 through YDk.
The write circuits 41 and 42 respectively apply a prescribed high voltage VPP for writing to the data buses DB-1 and DB-2 in a data write operation.
The two data buses DB-1 and DB-2 are provided in order to perform a data read operation in one memory cell array block and a data write operation in another memory cell array block.
The sensing amplifiers 43 and 44 respectively sense and amplify the currents in the data buses DB-1 and DB-2, and output the resultant signals to an external device in a data read operation.
Each memory cell array block MA includes a plurality of word lines and a plurality of bit lines (not shown in FIG. 6). One of the two row decoders (e.g., the row decoder XD1) is connected to one selected word line out of the plurality of word lines in the memory cell array block MA1. The other row decoder (e.g., the row decoder XD2) is connected to one selected word line out of the plurality of word lines in the memory cell array block MAk.
The row decoders XD1 and XD2 each output a prescribed word line selection signal indicating the selected word line in accordance with a signal level of a row selection portion of an input address signal.
The plurality of column decoders YD1, YD2, . . . , YDk each connect a selected bit line to the data bus DB-1 or DB-2 in accordance with a signal level of a column selection portion of the input address signal in a data write operation or a data read operation to or from the corresponding memory cell array block MA.
The plurality of switching circuits SW1, SW2, . . . , SWk-1 are each provided between each two adjacent memory cell array blocks MA to connect these two memory cell array blocks in series. For example, the switching circuit SW1 is provided between the memory cell array blocks MA1 and MA2, and the switching circuit SW2 is provided between the memory cell array blocks MA2 and MA3.
In more detail, the plurality of switching circuits SW1 through SWk-1 each include a plurality of switching devices (not shown in FIG. 6). Each switching device is provided between a word line in one of the corresponding memory cell array blocks MA and a word line in the other of the corresponding memory cell array blocks MA. The plurality of switching devices in each switching circuit are collectively controlled to be either on or off.
By turning off one of the switching circuits SW1 through SWk-1, the entirety of the plurality of memory cell array blocks MA1 through MAk is divided into two memory cell array block regions (i.e., a region including the memory cell array block MA1 and a region including the memory cell array block MAk), which are operable independently. By causing the row decoder XD1 to select one of the word lines in the memory cell array block MA1 and causing the row decoder XD2 to select one of the word lines in the memory cell array block MAk, a read operation and a write or erasure operation can be concurrently performed in the two memory cell array block regions. In addition, independent write operations to the two memory cell array block regions can be concurrently performed.
By turning off a different switching circuit, the number of memory cell array blocks included in each of the two memory cell array block regions can be arbitrarily changed.
However, the conventional nonvolatile semiconductor memory device 40 allows a write operation and an erasure operation to be performed to or from any memory cell array block MA. Accordingly, the conventional semiconductor memory device 40 does not solve a problem which is common to nonvolatile memory devices that the data in the memory cell array block can be inadvertently or illegally rewritten.
A nonvolatile semiconductor memory device according to the present invention includes a plurality of memory cell array blocks including a first memory cell array block to which a data write operation is performed or from which a data erasure operation is performed, and a second memory cell array block from which a data read operation is performed concurrently with the data write operation or the data erasure operation to or from the first memory cell array block; and a plurality of block lock setting devices respectively provided in correspondence with the plurality of memory cell array blocks for placing the second memory cell array block into a locked state in which a data write operation to and a data erasure operation from the second memory cell array block is prohibited.
In one embodiment of the invention, the plurality of block lock setting devices include floating gate MOS transistors or latch circuits.
In one embodiment of the invention, the nonvolatile semiconductor memory device further includes a memory operation and lock setting control device for performing a data write operation to, a data read operation and a data erasure operation from the first memory cell array block, and causing at least one of the block lock setting devices corresponding to the second memory cell array block to place the second memory cell array block into a locked state in which a data write operation to and a data erasure operation from the second memory cell array block is prohibited.
In one embodiment of the invention, the nonvolatile semiconductor memory device further includes a connection control device which is controlled by a control signal from the memory operation and lock setting control device for controlling a data read operation from the second memory cell array block and a data write operation to the first memory cell array block.
In one embodiment of the invention, the second memory cell array block includes at least one of information for which security is important or information which does not need to be rewritten.
In one embodiment of the invention, the plurality of memory cell array blocks each include a plurality of nonvolatile memory transistors to which information can be electrically written and from which information can be electrically read and erased, the plurality of nonvolatile memory transistors being arranged in a matrix having a plurality of rows and a plurality of columns, each of the plurality of nonvolatile memory transistors having a control gate, a drain and a source; a plurality of word lines each connected to the control gates of the nonvolatile memory transistors of a corresponding row among the plurality of rows; a plurality of bit lines each connected to the drains of the nonvolatile memory transistors of a corresponding column among the plurality of columns; a common source connected to sources of all the plurality of nonvolatile memory transistors; a plurality of row decoders each for outputting a word line selection signal in accordance with a signal level of a row selection signal portion of an input address signal; and a plurality of column decoders each for outputting a bit line selection signal in accordance with a signal level of a column selection signal portion of an input address signal. The plurality of memory cell array blocks include at least three memory cell array blocks.
Thus, the invention described herein makes possible the advantages of providing a nonvolatile semiconductor memory device for preventing data in a memory cell array block to be inadvertently or illegally rewritten.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.